1. Field of the Invention
The present invention relates to a time-division multiplex transmission network system in which data of a predetermined number of bits can be transmitted and received between at least one data transmitter and at least one data receiver constituting the network system, with a high reliability and with a high efficiency.
2. Description of the Prior Art
Conventional network systems are exemplified by a Japanese Patent Application Examined Open No. Sho 52-13367.
FIGS. 1, 2, and 3 show the network system disclosed in the above-identified Japanese Patent Application publication.
A synchronization signal generator 1 generates a clock signal having a constant period .tau. as shown in FIG. 2(a) and a third-order M-series code string repeating such an order as H, H, H, L, L, H, and H for each constant period T as shown in FIG. 2(b), modulates the M-series code in a pulse width modulation mode, and sends the modulated code signal to an address clock transmission line 3.
A data transmitter 5 comprises: a reception circuit 7 which receives the modulated code signal via the address clock transmission line 3 and demodulates it into the synchronization signal shown in FIG. 2(a) and code string signal shown in FIG. 2(b); a three-bit shift register 9, 11, and 13 which sequentially shifts the demodulated code string signal in synchronization with the demodulated synchronization signal; and a logic circuit 17 which opens a gate 15 when a logic operation of each output stage of the above-described shift register 9, 11, and 13 is carried out and when the logic operation results in a predetermined logic.
FIG. 3 shows each output signal state D1, D2, and D3 of the three-bit shift register 9, 11, and 13 and output signal state X of the logic circuit 17 for each synchronization signal. As shown in FIG. 3, seven combination patterns of the output signal levels "L" and "H" appear during the period T of the code string signal.
Hence, if one of the seven kinds of combination patterns in each data transmitter 5, e.g., H, H, L shown in FIG. 3 is an established condition of the logic circuit 17, the logic condition of the logic circuit 17 is established only once during the interval T of the above-described code string signal so that the gate 15 is opened and one bit data is sent from an input circuit 19 to a data transmission line 21.
Similarly, the data receiver 23 comprises: a reception circuit 25; a three-bit shift register 27, 29, and 31; and a logic circuit 33. When a predetermined combination pattern is produced during one period T of the above-described code string signal, the gate 35 is opened so that the data is fetched from the data transmission line 21 and a signal processing circuit 36 carries out a predetermined processing. In this way, mutual data transmission and reception is established between the transmitter 5 and receiver 23.
However, since in the conventional network system one bit of data is transmitted in synchronization with the synchronization signal with the respective gates 15, 35 opened when a predetermined address allocated to each of data transmitter and corresponding receiver appears, only one bit of information, e.g., on-and-off information is transmitted whenever the logic condition is established.
Since in the one-bit transmission method a parity bit cannot be added to the information, a reliability of data transmission in the network system is reduced.
In addition, if data comprising a plurality of bits are transmitted and received between a pair of data transmitter and receiver in the conventional network system, a plurality of addresses need to be allocated to each of the data transmitter and receiver or a single data need to be divided into a series of one-bit data and transmitted a plural number of times by one bit. Consequently, the combinations of the pair of data transmitter and receiver become complex and transmission time required for the whole data becomes longer.